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IMX219: Adjust PLL settings based on the number of MIPI lanes #6575
base: rpi-6.6.y
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Links to https://forums.raspberrypi.com/viewtopic.php?t=381663 For reference, driver changes and overlay changes need to be in separate patches. The overlay can be an override on the existing imx219 overlay to reduce duplication. My diff (which I can't test) doing that was
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drivers/media/i2c/imx219.c
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imx219->lanes == 2 ? imx219_pll : imx219_pll_4lane, | ||
imx219->lanes == 2 ? ARRAY_SIZE(imx219_pll) : ARRAY_SIZE(imx219_pll_4lane), | ||
NULL); | ||
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You're not handling any failures from this table write.
TBH you may as well move the IMX219_REG_CSI_LANE_MODE
register into the array and just return the value from cci_multi_reg_write, or pass &ret
as the last argument to cci_write
below.
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Applied your recommended changes in the latest commit
There's a missing line (another closing brace and semicolon) in the proposed fragment 202, but otherwise it looks okay. |
Removed overlay changes from this PR and updated driver based on 6by9's suggestion |
Can you give us a Signed-off-by line for the changes in your PRs (this and #6580)? Mine would be: |
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Done for both! |
drivers/media/i2c/imx219.c
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@@ -1553,4 +1574,4 @@ module_i2c_driver(imx219_i2c_driver); | |||
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MODULE_AUTHOR("Dave Stevenson <[email protected]"); | |||
MODULE_DESCRIPTION("Sony IMX219 sensor driver"); | |||
MODULE_LICENSE("GPL v2"); | |||
MODULE_LICENSE("GPL v2"); |
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This change is spurious and makes checkpatch sad.
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Should be fixed now :)
Signed-off-by: Peyton Howe <[email protected]>
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Any comments, @6by9? |
I'd hoped to test with a module, but it got stuck in customs (hopefully arriving tomorrow). Commit message could be fuller, and include Do the pixel rate numbers work out for frame rate control? sohonomura2020's post at https://forums.raspberrypi.com/viewtopic.php?p=2283325#p2283325 implies the new IMX219_REG_PLL_VT_MPY should be 0x57 = 87 and IMX219_REG_PLL_OP_MPY should be 0x5a = 90. Your patch has 88 and 91. My maths says that IMX219_REG_PLL_OP_MPY = 91 gives a link rate of 364MHz, whilst 90 gives a link rate of 360MHz. Neither is the driver value of 363MHz. The example does say EXCK_FREQ = 12MHz. Continuing the search, registers 0x110A/B are listed as max_pre_pll_clk_div / "Maximum Pre PLL divider value" with a value of 0x0D (14 decimal), so perhaps /4 is permitted. That would be worth a test, as amending the link frequency is a pain (we'd have to log a warning for the approximation if asked for the previously "supported" value). |
Still can tweak the exact PLL settings, but this adds the overlays and driver support needed for 4-lane operation. I have tested on my Pi5 and run with both 4-lane and 2-lane cameras simultaneously.